EPIC workshop on Photonic Integrated Circuits

The reverse supply chain: from the specifications driven by telecom industry and datacentres to the current technology functionality and capabilities.

High level representatives of the European, as well as Worldwide, Photonic Integrated Circuits (PICs) community met at the EPIC Workshop on Photonics Integrated Circuits 2015, hosted at the headquarter facilities of EVG at St. Florian am Inn, Austria on 9-10 June 2015. The program had an innovative scope, which was focused on reinforcing links between the different parts of the reverse supply chain of PICs in one of the applications which currently represents a big portion of this technologies forecasted members: Telecom and Datecentres applications. The attendance list was design towards the full coverage of the technological know-how of such supply chain: from the application driven specifications defined by some of the industrial worldwide  leaders,  to  optical  interconnect  manufacturers, equipment  and  packaging  experts, integrated  photonic  designers  and,  last,  but  specially  not  least,  wafer  level  fabrication  facilities.  On that point, the companies represented were Aifotec, Amicra, Bright Photonics, Corning, Eblana, EVG, ficonTEC, Finisar, Fraunhoffer HHU, Fujitsu, Ghent University, Glyndwr University, Huawei, HUBER+SUHNER Cube Optics, IBM, IHP Microelectronics, KIT, Linkra, LioniX, Luceda, Lumerical, Luxtera, Multiphoton Optics, Nanoscribe, Nanosystec, Oclaro, Optoscribe, PETRA, PhoeniX Software, PNO Consultants, SABIC Innovative Prastics, Smart Photonics, Southampton University, Spin 1 Networks, TE Connectivity, Technobis, Technospark Nanocenter, Tektronix, Tyndall National Institute, US Conec, Vario-optics, VTT, Yelo and Zeiss.

Increasing bandwidth and reducing power consumption remain goals for the data centre due to the ever increasing traffic demands. It is broadly accepted by now that PICs have the potential to solve some of the technological bottlenecks and offer improved network functionality. Ground-breaking advances  in  research  and  development  of  advanced PIC  technologies  are constantly occurring.

With the market opportunity in mind, the drive of the workshop was to discuss if the technologies advances were in line with some of the supply chain needs, such as:

  1. The scaling of photonics to high levels of integration with improved performance, power consumption and better process control at low cost
  2. The need of equipment and process towards wafer scale testing
  3. The incorporation of solutions for low cost standardized packaging
  4. Solving  electrical  interconnect  limits  in  Data  centres,  Supercomputers  and  ICs with  higher  capacity, lower cost optical interconnects

Ultimately, the aim is to discuss the state of the art and the technological development needed to satisfy the supply chain demands.

Challenges in Telecom and Data centre market
Digital society drives the rapid increase of high seed development of applications, traffic and broadband demands. This was evidenced by the market forecast presented by Torsten Wipiejewski, Advanced Assembly Technology Manager at Huawei, which concluded that between 2012 to 2014, the amount of internet users will be doubled, the data generated by them will increase by a factor and the amount of mobile devices will be multiplied by 4. This ever increase demands strives the need for ultra-high bandwidth solutions resulting in the need of the implementation of densely integrated optical links.

The main challenge for massive integration of such optical links, characteristic in the unique selling points of PICs, are still the cost,  as expressed by Bert Offrein, Manager Photonics Group IBM Research Zurich. This cost is mainly linked to the increased assembly efforts related to the large amount of components being integrated, the critical optical interfaces and the tight alignment tolerance. This is even a greater issue when compared with electronics solutions, which also do not bring the reliability and yield concerns of PICs due to its less maturity.

To that respect, Peter De Dobbelaere, VP Engineer at Luxtera, defined the goal for the PICs realistically compete with current solutions. Such goal was proposed as three-fold: (1) the development of PIC design infrastructure, including device models with behavioural models, and automated design tools for simulation, layout and design rule check; (2) further development of wafer manufacturing, driven by the  use of an standard wafer processing toolset; and (3) the further standardization of packaging, as well as, wafer and device level testing.

The need for further development of PICs as Interconnects
According to Jeroen Duis, Technology incubator and Engineering Manager at TE Connectivity, the next generation high bandwidth system designs focus on optimizing 4 driver indicators: (1) the density of data per optical fiber measured Gb/s/mm; (2) the power consumption or heat generation per data, in W/Gb/s; (3) the applied cost of connectivity solutions in $/Gbps/m; and (4) the density of data per Printed Circuit Board Assembly area: Gb/s/mm. To that respect, the research PIC research community continue to evolve the current technology, some of those developments were presented at the workshop by Dave Thomson, Senior Research Fellow, Southampton University. The goal, according to Takehiro Hayashi, Senior Marketing Manager at PETRA, is to aim 20mW/Gb power consumption by 2020.

Classic multimode solutions will continue to be lower cost, as clearly presented by Craig Thompson, Director Strategic Marketing at Finisar. However assuming that optical connections at 100 Gbps multimode can cover a length of up to 150 m, then only systems with less than 25.000 servers can use them. Hence, the conclusion of Jeroen Duis is that datacentres with more than 25.000 servers are a potential market for single mode, and those drive the PIC technology roadmap of TE Connectivity.

Innovation and standardization of packaging solutions are key to lower costs
The need for further standardization of assembly process was highlighted by Susmita Adhikari, Manager Product Placement at HUBER+SUHNER Cube Optics. On that point the PIC community of EPIC has created a Working Group, chaired by Peter O’Brien, Head of Packaging at Tyndall, and Pim Kat, CEO of Technobis, to work towards the development of standard and design rules to facilitate development, prototyping and manufacturing of cost effect packaged chips. Such working group has prepared a living document of design rules and agreements as a result of a collaboration activity with input required from all partners and disciplines (PIC designers, material providers, wafer level and device manufacturers, equipment supliers, etc) not favouring a particular company product or technology. One of the main conclusions of Peter O’Brien was that the development of standard packages is not the priority, but the solutions of making a flexible, yet standardized approach on how those devices can fit those standard packages. A potential solution was presented by Tobias Lamprecht, CTO at Vario-optics: the use of integrated planar polymer waveguides for packaging aiming for Cost effective, passive assembly of lasers, photodiodes and fibers.

The standardization document developed by the EPIC community has the goal of future implementations in software platforms, such as Phoenix or Luceda software packages.  On that line, a further collaboration between software providers was portrayed as a need by Twan Korthorst, CEO, PhoeniX Software. During his presentation, Twan Korthorst announced the collaboration between Mentori graphics, Lumerical and Phoenix Software towards the creation of an unified design flow for PIC design. Pieter Dumon, CTO at Luceda, showed how the current design software solutions focus on the reuse of IP and knowledge sharing in combination with the enabling of custom design flows and powerful scripting, facilitating the work of PIC designers and fabless companies such as Bright Photonics and VLC Photonics. Ronald Broeke, CEO at Bright Photonics, represented the user community of those software providers, and agreed on the need of a joint design flow solution in order to optimize design speed and quality.

Beyond the design, a further standardization on the equipment used for the assembly of PIC-based devices is needed. The requirements for such equipment were expressed by Guenter Hummelt, CTO at Nanosystec as four-fold: (1) efficient assembly processes; (2) short cycle times; (3) flexibility for various device types; and (4) capability to cope with shortcoming of parts. In order to satisfy those requirements, Gunther Hummelt showed the need for a roadmap towards full automation, which as of today suffers from several impeding factors such as the low production volumes currently demanded, the high equipment cost in relation to the low labor cost in Asia and the lack of standardization in the device designs. Ruth Houbertz, CEO at Multiphoton Optics, added that another one of the current challenges is bringing the optics closer to the PIC chips, resulting in size and cost reductions.

Another aspect that should not be forgotten is the lack of standardization and metrics on the tests processes used to validate the technology.  David Simms, CEO at Yelo, showed that in order to automatized those tests, some requirements have not yet being met such as: (1) a low cost pick and place system for small volumes; (2) an standard for the electrical pad sized, pitches and locations; and (3) the definition of a contact area for probe to press the device onto a heatsink for heat removal and temperature control.

The new Integrated Photonics Institute in the US
Michael Lebby, Photonics consultant & Professor Glyndwr University, provided an update of the status of the PIC Community in North America. Three consortia led by the universities of Central Florida, Southern California and New York were selected by the U.S. Department of Defense and submitted proposals during last February for creating a $220 million Integrated Photonics Institute for Manufacturing Innovation. Such Institute is aim to be a teaching factory The Integrated Photonics Institute would be a “teaching factory” providing foundry access, integrated design tools, automated packaging, assembly, testing and workforce development.  The winner is expected to be known during June 2015.

PIC manufacturing fitting the market needs
The attendance of the workshop counted with some of the main European representatives of the manufacturing services of the three main PIC technologies: Silicon Photonics, Indium Phosphide and TriPleX.

The manufacturing of Indium Phosphide PIC technology in Europe has incurred many changes in the recent years, thanks to the European funded project PARADIGM, with the aim of reducing costs by more than an order of magnitude and realizing more complex and capable designs possible than ever before. Indium Phosphide is the only mature PIC technology that can provide the epitaxial integration of lasers and hence it has important added value for the next generation of Telecom/Datacom transceivers. The PARADIGM project, which finalized earlier this year, was presented by Norbert Grote, Deputy Head of the Photonic Components Department at Fraunhofer HHI. The success of the project was evidenced by the current existence of a full ecosystem in InP, offering affordable access thanks to the use of Multi-project Wafer fabrication runs, design rules and low cost packaging approaches for the technology evaluation. To that respect, Mike Wale, Director Active Products Research at Oclaro, highlighted that while some important and successful steps have been made, some challenges still need to be overcome, such as: (1) the generic set of design rules available are more complex than an individual device design; (2) real customers need to meet real specifications, often very demanding, and require of certain amount of trials to reach the proof of concept; and (3) generic qualification is still not possible, as even if a design uses the standard design rules, it is not yet automatically qualified. These 3 challenges can be solved if further optimization of the industrialization of the accomplishments of the PARADIGM project are to be implemented. To that respect, Richard Visser, CEO at SMART Photonics, the leading SME in offering commercial Indium Phosphide PIC foundry services, presented their efforts on such industrialization.

The Silicon Photonics scenario is slightly different that InP, as thanks to the use of CMOS technology, it benefits from a more mature manufacturing process, although it can’t offer epitaxially integrated lasers. Most of the current efforts are based on further integration of electronics and photonics as well as the integration of lasers in a cost-effective way. When it comes to the integration of electronics and photonics, one of the main efforts is leaded by IHP, on the use of Photonics BiCMOS technology. Lars Zimmermann, Silicon Photonics Team Leader at IHP, presented the latest advances on such technology. Furthermore, to the views of  Wim Bogaerts, Professor at Ghent University and imec, Large Scale Integration at low cost is the next milestone for Silicon Photonics, although significant challenges are still need to be overcome, to name a few: further electronic integration, improvements in compound yield and low cost packaging solutions.

TriPleX technology is continuously being presented as the PIC platform able to produce ultra low-loss optical waveguiding, starting from 0.1 dB/m.  Arne Leinse, VP at LioniX, showed how this characteristic can be exploited in many applications, but also can be a solution for the packaging of the other PIC technologies with higher functionality. This is pursued in the EU funded project PHASTFlex, in which TriPleX technology is proposed for the realization of an interposer between an InP-based PIC an optical fiber array, reducing the pitch of the I/Os of the PIC by more than an order of magnitude.

EVG offers lithography and wafer bonding soltions thoughout the whole manufacturing chain.
The workshop was concluded with the presentation of Thomas Uhrmann, Director of Business Development at EVG, which showed their current and future solutions in the field of Wafer bonding, PIC patterning, heterogeneous integration, advanced packaging, 3D integration and wafer level packaging, among others.


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