Packaging and Testing Roadmap for Photonic Integration

The rapid developments in generic integration technology have led to a dramatic reduction of the cost of PIC development and manufacturing at low and medium volumes. This has not yet been followed by a similar development in the cost of packaging and testing, however.

For many  applications these costs could be significantly higher than the cost of the chip. Therefore, development of generic packaging and testing methods has high priority.

The key to such a generic approach is the definition of standards for the form factor and the position
of optical and electrical (dc and rf) output ports. Generic packages are most important for R&D, protoyping and low volumes. For special applications and high volume production, they may serve as a starting point, but they will have to be further optimized. For R&D, prototyping and low volumes JePPIX is working on a standard for two generic packages:

  1. A low cost test assembly which has fibres and electrical leads connected to the chip (<500 €
    for a single package). This package is suitable for chip testing but not for commercial applications.
  2. A medium cost high-performance package (target: 1000 € for packaging a single chip,
    100-200 € per package for larger volumes). This package will accommodate up to 10 optical
    ports, 10 rf ports (25 GHz) and > 30 dc ports. From a performance point of view this package
    is suitable for commercial applications. We expect that a packaging service will be offered
    via JePPIX starting 2017.

For these standards a template is available in the PDKs, so that designers using this template can be sure that it will fit the generic package. The standard is parameterized and complies with a small set of different chip dimensions (form factor) and a different number of optical and electrical ports.
With these generic packaging standards and the templates provided through the PDKs, application
specific requirements for the PIC can be addressed while enabling a design for packaging strategy.
Interested companies are advised to contact JePPIX (coordinator@jeppix.eu).

For chips that are designed with the generic packaging templates in the PDKs we are developing
standardized test setups. We expect that starting in 2017 open access to high-performance test
facilities can be provided via JePPIX. Further, we are jointly developing generic and semi-automatic equipment for on-wafer testing and chip validation with the foundries that will lead to a significant
cost reduction for qualification and testing. The first pieces of such equipment should also become
available in 2017.

More about the JePPIX roadmap.

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